The present invention relates to a semiconductor device based on the so-called chip-on-chip technology, and in particular to a circuit configuration on a chip constituting the device.
In the trend of increasing versatility and packing density in large scale integration (LSI) semiconductor devices, demands for incorporating various circuits different in their functions in an LSI package are increasing. However, it is difficult to integrate circuits, which are usually fabricated according to different technologies, on a common semiconductor substrate today. Such difficulty generally arises in the combinations of a MOS (metal oxide semiconductor) or CMOS (complementary MOS) type circuit and a bipolar type circuits; the combinations including a CMOS (complementary MOS) circuit and a TTL (transistor-transistor logic) circuit, a CMOS digital circuit and an analog integrated circuit such as an A/D (analog-to-digital) or D/A (digital-to-analog) converter, and a CMOS circuit and an ECL (emitter coupled logic) circuit. In principle, such a combination might be possible in a semiconductor chip. However, the benefits provided by the combination could not compensate for the probable complexities in the processes to produce it, and further, the expected yield of products provided by the combination would be extremely low.
Chip-on-chip technology has been proposed as a means for allowing such combinations while retaining the advantages of the existing MOS and bipolar technologies as they are. That is, individual semiconductor chips having respective different technology circuits such as mentioned above are combined in a stacked structure and provided with wirings for interconnecting them via respective corresponding terminals formed thereon. Generally, the upper chip is smaller than the lower chip. With the introduction of a chip-on-chip structure, each chip can be fabricated in the respective optimized processes as employed for the conventional MOS, CMOS or bipolar semiconductor device.
FIG. 1 is a perspective view illustrating a conceptual structure of a chip-on-chip semiconductor device. Referring to FIG. 1, a small semiconductor chip 200 (second chip) having an internal circuit (second internal circuit, namely a which is not shown) is mounted on a larger semiconductor chip 100 (first chip) having another internal circuit (first internal circuit which is not shown). A number of terminals 101 are formed at the peripheral region of the first chip 100. These terminals 101, each having a relatively large size of 100 micron square, for example, are used for the connections to the external circuits or power sources. At the inner region of the first chip 100 are formed a number of smaller terminals 102, each having a size of 10 micron square, for example. The terminals 102 are used for the interconnections between the chips 100 and 200. For instance, data signals output from the chip 100 to the chip 200 or input to the chip 100 from the chip 200 are transmitted through the terminals 102. Further, control signals or power voltages are supplied to the second internal circuit via the terminals 102. Therefore, each of the terminals 102 is wired to a corresponding terminal 201 on the second chip via a corresponding one of wiring lines 202. Each of the wiring lines 202 may be a thin film wiring line of aluminum, for example, formed by using conventional thin film and lithographic technologies.
Each of the chips 100 and 200 are subjected to individual functional tests in a separate condition before they are stacked into a chip-on-chip structure. Therefore, it is required that each of the chips 100 and 200 be provided with a circuit configuration allowing for individual testing. This involves two requirements: (1) since the output of each of the first and second internal circuits is open circuited during the individual test, any means to take out output signals from the internal circuit must be provided for each of the chips 100 and 200 to be tested by an external test circuit; and (2) in the internal circuit formed on a chip based on MOS technology, MOS transistors or CMOS inverters are generally used as the input means. The gates of these MOS transistors or CMOS inverters must tentatively be clamped at respective appropriate potentials so as not to be left floating during the individual test. This is because such floating gate MOS transistors or CMOS inverters are in unidentified logical states and would disturb the operation of the internal circuit, thereby making the test invalid. Moreover, if a number of floating gate CMOS inverters are used as the input means of an internal circuit, the power source or the relevant power supply line would be damaged by the extraordinary excess currents flowing through the floating gate CMOS inverters, because the power source or power supply lines has been designed to comply with the maximum current flowing during the transitions of the CMOS inverters in the normal operation condition. The abovementioned requirements are also applied to the second internal circuit as well, if the circuit on the second chip is fabricated based on the MOS technology.
It is easy to think of providing each of the terminals 102 and 201 with a sufficient area to accommodate a touch of a probe which is tentatively used for the connections between the relevant internal circuit to be tested and an external test circuit or power supply. However, the area of such a terminal is inevitable as large as 100 micron square, as mentioned above, and reduces the chip area to be allotted to device regions. Therefore, it is undesirable to form a number of such large terminals on a chip in view of chip area utilization, particularly, at the inner region of the chip 100 which should be used for forming as many functional elements therein such as transistors as possible.
Thus, it is desired to solve the problem of the tradeoff between the requirements for allowing the individual test prior to the stacking of the chips into an chip-on-chip structure and the reduction in the chip area utilization efficiency.